Access device and phase change memory combination structure in backend of line (beol)

ABSTRACT

A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

TECHNICAL FIELD

The present invention relates generally to a method, system, andcomputer program product for fabricating compute-in-memory capablesemiconductor devices. More particularly, the present invention relatesto a method, system, and computer program product for access device andphase-change memory combination structure.

BACKGROUND

Within the scope of the illustrative embodiments—

(a) A Memory Element: Refers to an element that is used to storedata/information. Many options exist here (including, for example, phasechange memory (PCM), MRAM, Resistive RAM, solid electrolyte memory,FeRAM, etc.), with one promising memory node material being PCM.

(b) A Rectifying Element or Access Device (AD): Since a transistor isnot provided at every crosspoint, a device is needed to rectify (exhibitnonlinearity). This ensures that the memory cells that lie on unselectedwordlines and bitlines are not inadvertently programmed or shorted toeach other and do not leak any significant amount of current.

A variety of diodes can be used for rectification. The illustrativeembodiments recognize that the quality of the diodes that can befabricated in middle-of-line (MOL) or back end of line (BEOL) lowertemperature processes are typically unacceptable because they have to bemade in amorphous or polycrystalline silicon that has much lowermobility. These considerations prevent the use of p-n junctions ineither single-crystal silicon or other silicon materials as rectifiersfor certain memory elements.

The von Neumann bottleneck is a limitation on throughput caused by thestandard personal computer architecture—the stored programcomputer—which is also known as the von Neumann architecture. In the vonNeumann architecture, programs and data are held in memory, theprocessor and memory are separate and data moves between the tworesulting in latency. The improvements in data processing circuits havemade data processing faster, whereas the improvements in memory elementshave focused on making memories denser rather than faster. In thatconfiguration, latency is a prevalent problem, as is the increasing idletime for data processing circuits awaiting data from the memoryelements. These problems are referred to as the limitations of vonNeumann architecture.

New memory and access device combinations are being explored to overcomethe limitations of von Neumann architecture. One of the potentialcandidates proposed by the illustrative embodiments to enable nativeneuromorphic computing (NNC) that includes a combination of phase changememory and an access device fabricated together as a semiconductordevice unit. The illustrative embodiments recognize that such acombination device could enable compute-in-memory operations criticalfor native neuromorphic computing.

SUMMARY

The illustrative embodiments provide a method, system, and computerprogram product. An embodiment provides a semiconductor device thatincludes a first access structure formed from a mixed ionic electronicconduction (MIEC) material. The device further includes a first side ofa first memory structure electrically coupled with a first side of thefirst access structure to form a combination device, wherein asubtractive etching process is applied to the combination device suchthat a surface of the combination device that is substantiallyorthogonal to a plane of a substrate of the semiconductor device iswithin a defined tapering tolerance.

An embodiment includes a method of fabricating the semiconductor device.

An embodiment includes a fabrication system to fabricate thesemiconductor device. The system includes one or more processors, one ormore computer-readable memories, and one or more computer-readablestorage devices, and program instructions stored on at least one of theone or more storage devices for execution by at least one of the one ormore processors via at least one of the one or more memories.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objectives and advantages thereof, willbest be understood by reference to the following detailed description ofthe illustrative embodiments when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 depicts an example simple compute-in-memory circuit that isachieved by a combined structure according to an illustrativeembodiment;

FIG. 2 depicts one example configuration in which two combinedstructures are stacked, each combining a memory and an AD structures inaccordance with an illustrative embodiment;

FIG. 3 depicts one example configuration in which two combinedstructures are fabricated separately in the same process, each combininga memory and an AD structures in accordance with an illustrativeembodiment;

FIG. 4 depicts a view of the combined structure resulting from onevariation of a subtractive etching process of fabrication where theetching is performed without spacers in accordance with an illustrativeembodiment;

FIG. 5 depicts a view of the combined structure resulting from anothervariation of a subtractive etching process of fabrication where theetching uses spacers in accordance with an illustrative embodiment;

FIG. 6 depicts a view of the combined structure resulting from a porefilling process of fabrication in accordance with an illustrativeembodiment;

FIG. 7 depicts a view of the combined structure resulting from amushroom process of fabrication in accordance with an illustrativeembodiment;

FIG. 8 depicts an example series of steps in a subtractive etchingprocess according to an illustrative embodiment;

FIG. 9 depicts another example series of steps in a subtractive etchingprocess according to an illustrative embodiment;

FIG. 10 depicts an example series of steps in a subtractive etchingprocess according to an illustrative embodiment;

FIG. 11 depicts another example series of steps in a subtractive etchingprocess according to an illustrative embodiment;

FIG. 12 depicts an example series of steps in a PCM-pore filling processaccording to an illustrative embodiment;

FIG. 13 depicts a continuation of process 1200 in accordance with anillustrative embodiment;

FIG. 14 depicts a continuation of process 1200 in accordance with anillustrative embodiment;

FIG. 15 depicts an example series of steps in a PCM mushroom processaccording to an illustrative embodiment;

FIG. 16 depicts a continuation of process 1500 in accordance with anillustrative embodiment;

FIG. 17 depicts a continuation of process 1500 in accordance with anillustrative embodiment; and

FIG. 18 depicts a continuation of process 1500 in accordance with anillustrative embodiment.

DETAILED DESCRIPTION

The illustrative embodiments recognize that patterning of a memoryelement and an AD element in a single patterning process is a difficultproblem to solve. Such a patterning process is one of the criticalenabling technologies for NNC. Therefore, a need exists for afabricating process to fabricate a combined memory and AD device.

The illustrative embodiments further recognize that in the case of PCM,the SET operation is gradual but the RESET operation is abrupt thus eachdevice node for NNC requires not one but two (memory+AD) combinationstructures. Therefore, an ability to pattern memory (e.g. a PCM device)and AD (e.g., a mixed ionic and electronic conduction (MIEC) device)structure together in a single etch process has distinct advantages.Therefore, a need exists for a fabricating process to fabricate two ormore combined memory and AD devices simultaneously in a singlefabrication process.

The illustrative embodiments used to describe the invention generallyaddress and solve the above-described needs and other problems relatedto fabricating an access device and phase-change memory combinationstructure. The illustrative embodiments provide a fabrication method foraccess device and phase-change memory combination structure.

An embodiment comprises a semiconductor device described herein. Anotherembodiment comprises a fabrication process for the contemplatedsemiconductor device and can be implemented as a software application.The software application implementing an embodiment can be configured asa modification of an existing semiconductor fabrication system—such as aphotolithography system, as a separate application that operates inconjunction with an existing semiconductor fabrication system, astandalone application, or some combination thereof. For example, theapplication causes the semiconductor fabrication system to perform thesteps described herein, to fabricate an access device and phase-changememory combination structure, as described herein.

For the clarity of the description, and without implying any limitationthereto, the illustrative embodiments are described using a specifictype of memory element (PCM) and a specific type of AD element (MIEC).Within the scope of the illustrative embodiments, an embodiment can beimplemented with a variety of similarly purposed elements, where suchelements pose similar fabrication problems as are recognized with PCMand MIEC.

Furthermore, simplified diagrams of the example structures, elements,and device(s) are used in the figures and the illustrative embodiments.In an actual fabrication of a proposed device, additional structuresthat are not shown or described herein, or structures different fromthose shown and described herein, may be present without departing thescope of the illustrative embodiments. Similarly, within the scope ofthe illustrative embodiments, a shown or described structure in theexample device may be fabricated differently to yield a similaroperation or result as described herein.

Differently shaded portions in the two-dimensional drawing of theexample structures, layers, and formations are intended to representdifferent structures, layers, and formations in the example fabrication,as described herein. The different structures, layers, and formationsmay be fabricated using suitable materials that are known to those ofordinary skill in the art as belonging to the same class of materialsdescribed herein.

A specific shape, location, position, or dimension of a shape depictedherein is not intended to be limiting on the illustrative embodimentsunless such a characteristic is expressly described as a feature of anembodiment. The shape, location, position, dimension, or somecombination thereof, are chosen only for the clarity of the drawings andthe description and may have been exaggerated, minimized, or otherwisechanged from actual shape, location, position, or dimension that mightbe used in actual photolithography to achieve an objective according tothe illustrative embodiments.

Furthermore, the illustrative embodiments are described with respect toa specific actual or hypothetical semiconductor device only as anexample. The steps described by the various illustrative embodiments canbe adapted for fabricating a variety of planar and non-planar devices ina similar manner, and such adaptations are contemplated within the scopeof the illustrative embodiments. The specific electrodes placements arealso used only as non-limiting examples to describe certain optionspossible with the illustrative embodiments. Those of ordinary skill inthe art will be able to use an embodiment to similarly provideelectrical access to a layer or structure in a similar manner, and suchusage is also contemplated within the scope of the illustrativeembodiments.

An embodiment when implemented in an application causes a fabricationprocess to perform certain steps as described herein. The steps of thefabrication process are depicted in the several figures. Not all stepsmay be necessary in a particular fabrication process. Some fabricationprocesses may implement the steps in different order, combine certainsteps, remove or replace certain steps, or perform some combination ofthese and other manipulations of steps, without departing the scope ofthe illustrative embodiments.

A device of an embodiment described herein, comprises substantialadvancement of the compute-in-memory capability that is needed for theadvancement of computing technologies, including but not limited toneuro-morphic computing. A manner of patterning a PCM type memoryelement and an MIEC type AD element as described herein is unavailablein the presently available methods. Thus, a substantial advancement ofsuch devices or data processing systems by executing a method of anembodiment is in an improved fabrication process for fabricating acombined memory and AD device in a single process step.

The illustrative embodiments are described with respect to certain typesof devices, electrical properties, structures, formations, layers,orientations, directions, steps, operations, planes, materials,dimensions, numerosity, data processing systems, environments,components, and applications only as examples. Any specificmanifestations of these and other similar artifacts are not intended tobe limiting to the invention. Any suitable manifestation of these andother similar artifacts can be selected within the scope of theillustrative embodiments.

The illustrative embodiments are described using specific code, designs,architectures, protocols, layouts, schematics, and tools only asexamples and are not limiting to the illustrative embodiments.Furthermore, the illustrative embodiments are described in someinstances using particular software, tools, and data processingenvironments only as an example for the clarity of the description. Theillustrative embodiments may be used in conjunction with othercomparable or similarly purposed structures, systems, applications, orarchitectures.

The examples in this disclosure are used only for the clarity of thedescription and are not limiting to the illustrative embodiments.Additional structures, operations, actions, tasks, activities, andmanipulations will be conceivable from this disclosure and the same arecontemplated within the scope of the illustrative embodiments.

Any advantages listed herein are only examples and are not intended tobe limiting to the illustrative embodiments. Additional or differentadvantages may be realized by specific illustrative embodiments.Furthermore, a particular illustrative embodiment may have some, all, ornone of the advantages listed above.

With reference to FIG. 1, this figure depicts an example simplecompute-in-memory circuit that is achieved by a combined structureaccording to an illustrative embodiment. A MIEC AD structure describedherein operates as a diode depicted in circuit 100. Memory module Mj isa memory element described with respect to a combined structure of theillustrative embodiments. Mj can be formed using PCM or other type ofmemory element, e.g., CBRAM.

The simplified circuit depicted in circuit 100 is not intended to belimiting on the types of combined structures that can be formed using anembodiment. Those of ordinary skill in the art will be able to adapt anexample device described herein—which achieves the simple circuit 100 ofthis figure—to form more complex circuits in a similar manner using thedescribed structure. Such adaptations are contemplated within the scopeof the illustrative embodiments.

With reference to FIG. 2, this figure depicts one example configurationin which two combined structures are stacked, each combining a memoryand an AD structures in accordance with an illustrative embodiment.

A combination of one AD structure, e.g., one MIEC layer 202, and onememory element structure, e.g., one PCM layer 204 forms combinedstructure 200—a building block—according to an embodiment. Any number ofsuch combinations can be stacked in the manner depicted in FIG. 2.

A distinctive feature of each combined structure 200 according to theillustrative embodiments is that MIEC layer 202 in any instance ofcombined structure 200 is substantially non-tapering from the bottom tothe top of said layer 202. Stated another way, the sides of layer 202other than the sides of layer 202 shown contacting metal layers aresubstantially perpendicular relative to the plane of the contact withthe metal layers. Patterning MIEC layers with substantially verticalwalls is a difficult problem, and is achieved by a process describedherein to fabricate combined structure 200.

The building block combined structure 200 can include one or moresuitable layers or structures intervening between structures 202 and 204to form an electrically conducting path between structures 202 and 204.Layer 206 is such a layer and is formed by depositing a suitable metalduring the fabrication process.

Similarly, suitable conducting structures or layers may be formed onstructures 202 and 204 to allow electrical connectivity to combinedstructure 200 from an external circuit. Layers 208, 210, and 212depicted in FIG. 2 are examples of such conducting structures and may beformed by depositing the same or different conducting materials.

For example, layer 208 may be formed as a bottom electrode coupling toMIEC 202 and layer 210 may be formed as a top electrode coupling withPCM 204. Alternatively, layer 210 may be similar to layer 206 and couplePCM 204 with another instance of MIEC 202. Layer 212 may be formed asthe top electrode in such a combination.

An instance of structure 208, 210, or 212 may be formed on any of thesides of structure 202 that are not facing towards, or otherwiseconnecting to, a side of structure 204 in a non-stacked configuration.An instance of structure 208, 210, or 212 may be formed on any of thesides of structure 204 that are not facing towards, or otherwiseconnecting to, a side of structure 202 in a non-stacked configuration.

With reference to FIG. 3, this figure depicts one example configurationin which two combined structures are fabricated separately in the sameprocess, each combining a memory and an AD structures in accordance withan illustrative embodiment. Each of structures 302 and 304 is similar toone instance of combined structure 200 in FIG. 2. In each of combinedstructures 302 and 304, structures 202, 204, 206, 208, 210, and 212 arefabricated and operate in a manner similar to the fabrication andoperations of similarly numbered structures in FIG. 2.

For example, layer 208 may be formed as a bottom electrode coupling toMIEC 202 in combination device 302 and layer 210 may be formed as a topelectrode coupling with PCM 204 in combination device 302. In device304, layer 210 may be the bottom electrode of MIEC 202 in combinationdevice 304. Layer 212 may be formed as the top electrode in combinationdevice 304.

Without implying any limitation thereto, structures 302 and 304 may befabricated in parallel on the same substrate. One reason to formparallel combined structures of FIG. 3 instead of stacked combinedstructure of FIG. 2 is to reduce capacitance between the layers of thecombined structures. Another reason is to reduce aspect ratio of thepillar to be etched.

With reference to FIG. 4, this figure depicts a view of the combinedstructure resulting from one variation of a subtractive etching processof fabrication where the etching is performed without spacers inaccordance with an illustrative embodiment. Stacked combination device400 corresponds to stacked combination device 200 instances depicted inFIG. 2. Parallel combination devices 450 corresponds to combinationdevice 302 and 304 instances depicted in FIG. 3.

Note that the entire stacked combination device 400 and each parallelcombination device in 450 has walls or vertical surfaces that aresubstantially perpendicular to the plane of substrate 401. Thesevertical surfaces include vertical surfaces of MIEC layers 402, whichare also formed in substantially vertical manner using one form ofsubtractive etching process according to an embodiment. In this form ofsubtractive etching, no spacer material is needed as the layers areprogressively etched from top metal hard mask (HM) layer 412 up to butnot including bottom electrode layer 408.

In function, form, and materials, layer 402 corresponds to layer 202,layer 404 corresponds to layer 204, layer 406 corresponds to layer 206,layer 408 corresponds to layer 208, layer 410 corresponds to layer 210,and layer 412 corresponds to layer 212. Substrate 401 is of any suitablesubstrate material, commonly but not necessarily Silicon (Si).Dielectric 403 is any suitable dielectric material, such as includingbut not limited to silicon oxide (SiO2 or “oxide”).

With reference to FIG. 5, this figure depicts a view of the combinedstructure resulting from another variation of a subtractive etchingprocess of fabrication where the etching uses spacers in accordance withan illustrative embodiment. Stacked combination device 500 correspondsto stacked combination device 200 instances depicted in FIG. 2. Parallelcombination devices 550 corresponds to combination device 302 and 304instances depicted in FIG. 3.

Note again that the entire stacked combination device 500 and eachparallel combination device in 550 has walls or vertical surfaces thatare substantially perpendicular to the plane of substrate 401. Thesevertical surfaces include vertical surfaces of MIEC layers 402, whichare also formed in substantially vertical manner using one form ofsubtractive etching process according to an embodiment.

In this form of subtractive etching, spacer 505 material is deposited ina stepped manner as the layers are progressively etched from top metalhard mask (HM) layer 412 up to but not including bottom electrode layer408. Spacer 505 can be formed using any suitable insulator materialknown to be used for creating an etching resistant barrier. Additionallayers may exist above the metal HM layer 412, e.g., a photo-resist (PR)layer, an anti-reflective coating (ARC), and/or an optical planarizinglayer (OPL).

With reference to FIG. 6, this figure depicts a view of the combinedstructure resulting from a pore filling process of fabrication inaccordance with an illustrative embodiment. Any etching of any layer incombination device 600 or 650 can be performed with or without spacersas described in FIGS. 4 and 5.

Stacked combination device 600 corresponds to stacked combination device200 instances depicted in FIG. 2. combination device 650 corresponds toany one of parallel combination devices 302 and 304 depicted in FIG. 3.

Portion 601 can be formed in a manner of a corresponding portion in FIG.4 or FIG. 5. For example, the layers in portion 601 can be patternedusing a combination of lithography, reactive ion etching (RIE),dielectric filling, and chemical-mechanical planarization (CMP) methodsof fabrication.

With reference to stacked combination devices 600, dielectric 602 isdeposited over metal 406 layer. Dielectric 602 may be the same as ordifferent from dielectric 403. Pore 604 is formed in dielectric 602using any suitable pore forming method known to those of ordinary skillin the art. Pore 604 is essentially a tapered hole reaching across thefull depth of dielectric 602 and exposing metal 406 below dielectric602. Pore 604 is filled with PCM material 404.

Portion 603 is formed over PCM-filled pore 604 in a manner of acorresponding portion in FIG. 4 or FIG. 5. The techniques usable to formportion 603 can be similar to the techniques used in forming portion601.

Again, second instance of dielectric 602 is deposited over secondinstance of metal 406 layer. Second instance of pore 604 is formed insecond instance of dielectric 602 using any suitable pore forming methodknown to those of ordinary skill in the art. Second instance of pore 604is filled with PCM material 404.

Any number of combination devices can be stacked in this manner usingpore filling method of fabrication of combination devices. Over the laststacked combination device, top electrode layer 612 is formed using anysuitable fabrication method, including but not limited to deposition,patterning, or planting.

Cs 650 is essentially a single combination device where portion 651corresponds to portion 601 of stacked combination devices 600. Thetechniques usable to form portion 651 can be similar to the techniquesused in forming portion 601.

Dielectric 602 is deposited over metal 406, pore 604 is formed, and PCMmaterial 404 is filled in pore 604 in a similar manner as in stackedcombination devices 600. Top electrode 612 is formed over PCM-filledpore 604.

With reference to FIG. 7, this figure depicts a view of the combinedstructure resulting from a mushroom process of fabrication in accordancewith an illustrative embodiment. Any etching of any layer in combinationdevice 700 or 750 can be performed with or without spacers as describedin FIGS. 4 and 5.

Stacked combination device 700 corresponds to stacked combination device200 instances depicted in FIG. 2. combination device 750 corresponds toany one of parallel combination devices 302 and 304 depicted in FIG. 3.

With reference to stacked combination devices 700, dielectric 602 isdeposited over metal 406 layer. Pore 704 is formed in dielectric 602using any suitable pore forming method known to those of ordinary skillin the art. Pore 604 is filled with a conducting material, such as ametal, to form bottom electrode 704 of PCM 404. PCM 404 formed overbottom electrode 704 in this manner resembles a mushroom, hence the nameof the process. Any number of combination devices can be stacked in thismanner using mushroom PCM method of fabrication of combination devices.

The top of PCM 404 in any given combination device can be metalized withlayer 410. Metal layer 410 may either couple with another MIEC layer402, as in combination device 700 when additional combination devicesare stacked above as in combination devices 700, or with top electrode612 at the last stacked combination device in combination devices 700 orthe single combination device as in 750.

With reference to FIG. 8, this figure depicts an example series of stepsin a subtractive etching process according to an illustrativeembodiment. Assume that the objective is to form structure 400 of FIG.4—a stacked combination device without spacers. At the beginning ofprocess 800, suppose that layers 801 have been formed using a suitablemethod of fabrication. Layers 801 include substrate 401, bottomelectrode 408, MIEC 402, metal 406, PCM 404, metal 410, MIEC 402, metal406, PCM 404, and metal HM 412. Above layers 801, oxide layer 803, OPL805, ARC 807 and PR layer 809 have been deposited.

The process begins at step 802 by patterning PR layer 809 into a shape.At step 804, the pattern is transferred to ARC 807 and OPL 805 layers,with PR layer 809 being removed (subtracted). The pattern transfermaintains the substantially vertical orientation of the side walls beingformed at those layers.

At step 806, the lithography continues and the pattern is transferred tooxide 803 and metal HM 412, with ARC layer 807 being removed(subtracted). The pattern transfer maintains the substantially verticalorientation of the side walls being formed at those layers.

At step 808, OPL 805 is stripped (removed or subtracted). Thereafter,the lithography continues, oxide layer 803 is subtracted, and the samepattern is transferred in step 810 to subsequently lower layers untilthe etching reaches bottom electrode 408. The etched sides of thevarious layers above layer 408 are encapsulated in a dielectricmaterial, e.g., dielectric 403. One or more of the horizontal surfacesof the encapsulated structure may also be polished.

With reference to FIG. 9, this figure depicts another example series ofsteps in a subtractive etching process according to an illustrativeembodiment. Assume that the objective is to form structure 500 of FIG.5—a stacked combination device with spacers.

Process 900 begins after process 800 has formed layers 801 and performedsteps 802, 804, and 806. Process 900 picks up after step 806 of FIG. 8.

At step 902, PCM 404 0 below HM 412 is etched in the same pattern as HM412 and oxide 803 above. A suitable spacer material 911 is deposited toprotect the walls of HM 412 and PCM 404 exposed from the etching. Spacer911 is a part of spacer 505 in FIG. 5. Adding spacer 911 changes thepattern for the layers below PCM 404.

At step 904, layers 406 and 402 below PCM 404 are etched according tothe new pattern while maintaining substantially vertical etched walls atlayers 406 and 402. At step 906, a suitable spacer material 913 isdeposited to protect the walls of layers 406 and 402 exposed from theetching. Spacer 913 is another part of spacer 505 in FIG. 5. Addingspacer 913 further changes the pattern for the layers below MIEC layer402.

At step 908, layers 410 and 404 below MIEC layer 402 are etchedaccording to the new pattern while maintaining substantially verticaletched walls at layers 410 and 404. At step 910, a suitable spacermaterial 915 is deposited to protect the walls of layers 410 and 404exposed from the etching. Spacer 915 is another part of spacer 505 inFIG. 5. Adding spacer 915 further changes the pattern for the layersbelow PCM layer 404.

At step 912, layers 406 and 402 below PCM layer 404 are etched accordingto the new pattern while maintaining substantially vertical etched wallsat layers 406 and 402. If further stacked combination devices existedbelow layer 402 etched at step 912, another spacer would be deposited.Because in the depicted example, back electrode layer 408 has beenreached by the etching of step 912, no further etching has to occur.Accordingly, no additional spacer is needed to protect the walls oflayers 406 and 402 exposed from the etching of step 912. Thereafter, theetched sides of the various layers above layer 408 are encapsulated in adielectric material, e.g., dielectric 403. One or more of the horizontalsurfaces of the encapsulated structure may also be polished.

With reference to FIG. 10, this figure depicts an example series ofsteps in a subtractive etching process according to an illustrativeembodiment. Assume that the objective is to form structure 450 of FIG.4—parallel combination devices without spacers. Process 1000 progressesessentially as process 800 in FIG. 8, except that the patterning formsparallel structures with two or more PR layer structures 809 beingformed as shown instead of a single PR layer structure 809 in FIG. 8.

Thereafter, step 1004 corresponds to step 804 albeit patterning multipleparallel vertical structures instead of a single stacked verticalstructure. Layers 809, 807, 805, and 803 are subtracted as the patternprogresses downwards through the layers in substantially the manner ofprocess 800. At step 1010, corresponding to step 810 in FIG. 8,dielectric 403 is filled not only around the parallel structures butalso between the parallel structures as shown.

With reference to FIG. 11, this figure depicts another example series ofsteps in a subtractive etching process according to an illustrativeembodiment. Assume that the objective is to form structure 550 of FIG.5—parallel combination devices with spacers. Process 1100 progressesessentially as process 900 in FIG. 9, except that the patterning formsparallel structures with two or more oxide layer structures 803 beingformed as shown instead of a single oxide layer structure 803 in FIG. 9.

Thereafter, step 1104 corresponds to step 904 albeit patterning multipleparallel vertical structures instead of a single stacked verticalstructure. Step 1104 also deposits spacer 911 not only on the verticalwalls but on all etched areas as shown. Step 1106 etches the spacermaterial from the horizontal areas atop the vertical structures andmetal layer 406.

Step 1110 corresponds to step 910 in FIG. 9, where the bottommost metallayer 406 and MIEC layer 402 are etched before reaching back electrodelayer 408 at each of the parallel structures. At step 1112,corresponding to step 912 in FIG. 9, dielectric 403 is filled not onlyaround the parallel structures but also between the parallel structuresas shown.

With reference to FIG. 12, this figure depicts an example series ofsteps in a PCM-pore filling process according to an illustrativeembodiment. The fabrication of any of the combination devices describedherein—stacked or parallel, with or without spacer, or some combinationthereof—is possible with process 1200, assume that the objective is toform structure 400 of FIG. 4—a stacked combination device withoutspacers. At the beginning of process 1200, the process forms layers 1201using a suitable method of fabrication. Layers 1201 include substrate401, bottom electrode 408, MIEC 402, and metal 406. Above metal layer406, oxide layer 803, OPL 805, ARC 807 and PR layer 809 have beendeposited. The PCM layers are not yet formed, as they will be formed bypore filling in process 1200.

The process begins at step 1202 by patterning PR layer 809 into a shape,such as by using a suitable photolithography mask. At step 1204, thepattern is transferred to ARC 807 and OPL 805 layers, with PR layer 809being removed (subtracted). The pattern transfer maintains thesubstantially vertical orientation of the side walls being formed atthose layers.

At step 1206, the lithography continues and the pattern is transferredto oxide 803 and metal HM 412, with ARC layer 807 being removed(subtracted). The pattern transfer maintains the substantially verticalorientation of the side walls being formed at those layers.

At step 1208, OPL 805 is stripped (removed or subtracted). Thereafter,the lithography continues, oxide layer 803 is subtracted, and the samepattern is transferred in step 1210 to subsequently lower layers untilthe etching reaches bottom electrode 408. Process 1200 continues in FIG.13.

With reference to FIG. 13, this figure depicts a continuation of process1200 in accordance with an illustrative embodiment. At step 1212, theetched sides of the various layers above layer 408 are encapsulated in adielectric material, e.g., dielectric 403. One or more of the horizontalsurfaces of the encapsulated structure may also be polished.

At step 1214, dielectric 602 is deposited above the encapsulatedstructure resulting from step 1212. In step 1214, pore 604 is formed indielectric 602. At step 1216, pore 604 is filled with PCM material 404.As can be seen in step 1216, the fill is not exact and some PCM material404 may remain above the top level of pore 604. Step 1218 performs CMPor otherwise etches back that PCM material 404 which is overflowing pore604. PCM material 404 makes electrical contact with metal layer 406below and is available to make electrical contact with a layer that willbe deposited above in step 1220.

At step 1220, a set of layers for the next stacked combination deviceare deposited above PCM-filled pore 604. The set of layers includesmetal layer 410, MIEC layer 402, metal layer 406, and metal HM 412.Process 1200 continues in FIG. 14.

With reference to FIG. 14, this figure depicts a continuation of process1200 in accordance with an illustrative embodiment. At step 1222, HMlayer 412 is etched. Layers 406, 402, and 410 below HM 412 aresubtractively etched as described herein. The etched sides of thevarious layers above PCM-filled pore 604 are encapsulated in adielectric material, e.g., dielectric 403. One or more of the verticalsurfaces of the encapsulated stacked structure may also be polished.

At step 1224, dielectric 602 is deposited above the stacked encapsulatedstructure resulting from step 1222. In step 1224, pore 604 is formed indielectric 602. Pore 604 is filled with PCM material 404. CMP or otheretchback process is performed to remote that PCM material 404 which isoverflowing pore 604. PCM material 404 makes electrical contact withmetal layer 406 below and is available to make electrical contact with alayer that will be deposited above in step 1226. Assuming that no morecombination devices are to be stacked above, PCM-filled pore 604 can nowbe capped with top electrode 612.

With reference to FIG. 15, this figure depicts an example series ofsteps in a PCM mushroom process according to an illustrative embodiment.The fabrication of any of the combination devices describedherein—stacked or parallel, with or without spacer, or some combinationthereof—is possible with process 1200, assume that the objective is toform structure 400 of FIG. 4—a stacked combination device withoutspacers. At the beginning of process 1500, the process forms layers1201, as in FIG. 12, using a suitable method of fabrication. Layers 1201include substrate 401, bottom electrode 408, MIEC 402, and metal 406.Above metal layer 406, oxide layer 803, OPL 805, ARC 807 and PR layer809 have been deposited. The PCM layers are not yet formed, as they willbe formed by pore filling and mushrooming in process 1500.

The process begins at step 1502 by patterning PR layer 809 into a shape,such as by using a suitable photolithography mask. At step 1504, thepattern is transferred to ARC 807 and OPL 805 layers, with PR layer 809being removed (subtracted). The pattern transfer maintains thesubstantially vertical orientation of the side walls being formed atthose layers.

At step 1506, the lithography continues and the pattern is transferredto oxide 803 and metal HM 412, with ARC layer 807 being removed(subtracted). The pattern transfer maintains the substantially verticalorientation of the side walls being formed at those layers.

At step 1508, OPL 805 is stripped (removed or subtracted). Thereafter,the lithography continues, oxide layer 803 is subtracted, and the samepattern is transferred in step 1510 to subsequently lower layers untilthe etching reaches bottom electrode 408. Process 1500 continues in FIG.13.

With reference to FIG. 16, this figure depicts a continuation of process1500 in accordance with an illustrative embodiment. At step 1512, theetched sides of the various layers above layer 408 are encapsulated in adielectric material, e.g., dielectric 403. One or more of the horizontalsurfaces of the encapsulated structure may also be polished.

At step 1514, dielectric 602 is deposited above the encapsulatedstructure resulting from step 1512. In step 1514, pore 604 is formed indielectric 602. At step 1516, pore 604 is filled with bottom electrodematerial 408. Note that a material different than material 408 may beused to fill pore 604 so long as the other material is suitable forforming an electrode. The fill may not be exact and some bottomelectrode material 408 may remain above the top level of pore 604. Step1518 performs CMP or otherwise etches back that bottom electrodematerial 408 which is overflowing pore 604. Bottom electrode material408 makes electrical contact with metal layer 406 below and is availableto make electrical contact with a layer that will be deposited above instep 1820.

At step 1520, PCM layer 404 is deposited over electrode material filledpore 604. Metal layer 410 is deposited above PCM layer 404. Bottomelectrode material 408 in pore 604 thus forms the bottom electrode ofmushroomed PCM 404. Process 1500 continues in FIG. 17.

With reference to FIG. 17, this figure depicts a continuation of process1500 in accordance with an illustrative embodiment. At step 1522, metallayer 410 and PCM 404 are etched. The etched sides of the various layersabove filled pore 604 are encapsulated in a dielectric material, e.g.,dielectric 403. One or more of the vertical surfaces of the encapsulatedstacked structure may also be polished. The top of metal layer 410 mayalso be subjected to CMP to enable further deposition as shown in FIG.18. Process 1500 continues in FIG. 18.

With reference to FIG. 18, this figure depicts a continuation of process1500 in accordance with an illustrative embodiment. At step 1524,another stack of layers is deposited to form a stacked combinationdevice above the encapsulated structure resulting from step 1522. MIEClayer 402, metal layer 406 are deposited above the encapsulatedstructure of step 1522, and etched, encapsulated, and polished asdescribed herein. Dielectric 602 is deposited above resulting stackedencapsulated structure. Pore 604 is formed in dielectric 602. Pore 604is filled with bottom electrode material 408 or another suitableelectrode material. CMP or other etchback is performed to remove thatelectrode material 408 which is overflowing pore 604.

Electrode material 408 in pore 604 makes electrical contact with metallayer 406 below and is available to make electrical contact with a layerthat will be deposited above.

PCM layer 404 is deposited over the stacked electrode material filledpore 604. Metal layer 410 is deposited above PCM layer 404. Layers 404and 410 are subtractively etched, encapsulated, and polished asdescribed herein. Bottom electrode material 408 in stacked pore 604 thusforms the bottom electrode of stacked mushroomed PCM 404. Assuming thatno more combination devices are to be stacked above, top metal layer 410can now be capped with top electrode 612.

While certain steps and processes are described with certain structures,it is to be understood that the steps and/or processes can be adapted tofabricate any of the structure variations described herein within thescope of the illustrative embodiments. While certain materials are usedin multiple layers or structures, it is to be understood that substitutematerials or different but functionally equivalent materials can be usedin place of the described materials at any layers described hereinwithin the scope of the illustrative embodiments. While certainfabrication methods have been used at certain steps, it is to beunderstood that a fabrication method may be omitted, added, or modifiedat a described step to achieve functionally similar result from thesemiconductor structure within the scope of the illustrativeembodiments. While certain operations are described as a “step,” severaloperations can be combined together to form a single fabrication step ina process described herein. While certain orientations have beenreferred to as “top” and “bottom” with reference to an example verticalorientation of the proposed device, it is to be understood that thedevice can be reoriented laterally such that the top and bottom becomeleft/right or right/left, or bottom and top, or front/back orback/front, as the reorientation case may be.

Thus, a semiconductor device, fabrication method therefor, and afabrication system or apparatus therefor using a software implementationof the method, are provided in the illustrative embodiments for accessdevice and phase-change memory combination structure and other relatedfeatures, functions, or operations. Where an embodiment or a portionthereof is described with respect to a type of semiconductor device, thefabrication method, system or apparatus, the software implementation, ora portion thereof, are adaptable or configurable for use with adifferent manifestation of that type of device.

The present invention may be a semiconductor device, system, a method,and/or a computer program product at any possible technical detail levelof integration. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention. A computer readable storage medium, including but notlimited to computer-readable storage devices as used herein, is not tobe construed as being transitory signals per se, such as radio waves orother freely propagating electromagnetic waves, electromagnetic wavespropagating through a waveguide or other transmission media (e.g., lightpulses passing through a fiber-optic cable), or electrical signalstransmitted through a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network.

What is claimed is:
 1. A semiconductor device comprising: a first accessstructure formed from a mixed ionic electronic conduction (MIEC)material; a first side of a first memory structure electrically coupledwith a first side of the first access structure to form a combinationdevice, wherein a subtractive etching process is applied to thecombination device such that a surface of the combination device that issubstantially orthogonal to a plane of a substrate of the semiconductordevice is within a defined tapering tolerance.
 2. The semiconductordevice of claim 1, wherein the subtractive etching process is a singlestep in the fabrication process.
 3. The semiconductor device of claim 1,further comprising: a first electrode electrically coupled with a secondside of the first access structure; and a second electrode electricallycoupled with a second side of the first memory structure.
 4. Thesemiconductor device of claim 1, further comprising: a pore in adielectric material deposited over the first access structure; and aPhase-Change memory (PCM) material forming the first memory structurefilled in the pore, wherein the pore is configured to enable anelectrical coupling between the first memory structure and the firstaccess structure.
 5. The semiconductor device of claim 1, furthercomprising: a pore in a dielectric material deposited over the firstaccess structure; an electrode formed by filling an electrode materialin the pore, wherein the pore is configured to enable an electricalcoupling between a first end of the electrode and the first accessstructure, and wherein the first memory structure is formed such thatthe first surface of the first memory structure is in an electricalcoupling with a second end of the electrode.
 6. The semiconductor deviceof claim 1, further comprising: a second access structure formed fromthe MIEC material stacked on a second side of the memory structure,wherein the second side of the first memory structure is electricallycoupled with a second side of the second access structure; and a firstside of a second memory structure electrically coupled with a first sideof the second access structure.
 7. The semiconductor device of claim 1,further comprising: a first electrode electrically coupled with a secondside of the first access structure; and a second electrode electricallycoupled with a second side of the second memory structure.